Inject harmonic loads on an LV bus, watch IEEE 519‑2022 PCC compliance in real time, design and verify detuned capacitor banks by adjusting tuning frequency and individual harmonic orders, track parallel resonance and read out transformer harmonic derating per IEEE C57.110 — for plant‑design verification and harmonic‑mitigation design.
Login & Enter the SynthesiserSix live study areas — drag a slider, see every downstream effect immediately.
Individual harmonic sliders for h = 2…50. Live spectrum bars, THDv and THDi update as you drag. Auto-harmonic presets for common non-linear loads.
Enter your transformer nameplate, no-load loss, load loss and short-circuit MVA. See LV bus voltage, harmonic impedance Z(h) and available fault current.
Live compliance vs. TDD limits with the correct Isc/IL bracket at the PCC. Every finding cites the standard and clause.
Switch capacitor banks on / off — plain PFC or detuned (7 %, 14 %, 5.67 %). See the Z(h) peak move, resonant harmonic order and capacitor over‑voltage risk.
C57.110 capability curve, K-factor, harmonic loss factor FHL, eddy-current loss uplift and estimated hot-spot temperature.
Extra kW lost as heat, projected annual kWh and cost of the harmonic burden. Compare "as-is" against a proposed detuned or AHF solution.
Only the standards the tool actually references — harmonic compliance and transformer capability.
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